现任中国计算机学会监事长、曾任常务理事、容错计算专业委员会主任；Journal of Computer Science and Technology (JCST)副主编；Journal of Electronic Testing: Theory and Applications (JETTA) 和Journal of Low Power Electronics (JOLPE) 编委；IEEE Asia and Pacific Regional TTTC Vice-Chair；IEEE ATS Steering Committee Chair；担任IEEE VTS/DATE/PRDC/ASP-DAC等国际学术会议程序委员会委员。
代表论著
已发表的学术性著作选列： [1] 李晓维, 吕涛, 李华伟, 李光辉 著《数字集成电路设计验证——量化评估, 激励生成, 形式化验证》, 科学出版社, 2010年5月, 518千字, 411页 [2] 李晓维, 韩银和, 胡瑜, 李佳 著《数字集成电路测试优化——测试压缩, 测试功耗优化,测试调度》, 科学出版社, 2010年6月, 433千字, 344页 [3] 李晓维, 胡瑜, 张磊, 鄢贵海 著《数字集成电路容错设计——容缺陷/故障, 容参数偏差,容软错误》, 科学出版社, 2011年4月, 546千字, 433页 [4] Xiang Fu, Huawei Li, Xiaowei Li, “Testable Path Selection and Grouping for Faster Than At-Speed Testing”,IEEE Transactions on VLSI Systems, Vol.11, No.02, February 2012, pp.236-247 [5] Guihai Yan, Yingmin Li, Yinhe Han, Xiaowei Li, Xiaoyao Liang, “SAAS+RAAS: a Hybrid Application Scheduling Scheme using Mixed Voltage Regulators for DVFS in a Multicore Architecture”, IEEE The High-Performance Computer Architecture Symposium (HPCA-18), February 25-29, 2012, New Orleans, Louisiana, USA [6] Minjin Zhang, Huawei Li, Xiaowei Li, “Path Delay Test Generation Toward Activation of Worst Case Coupling Effects”, IEEE Transactions on VLSI Systems, Vol.10, No.11, November 2011, pp.1969-1982 [7] Ying Zhang, Huawei Li, Yinhua Min, Xiaowei Li, “Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects”, IEEE Transactions on VLSI Systems, Vol.10, No.10, October 2011, pp.1787-1800 [8] Guihai Yan, Yinhe Han, Xiaowei Li, “SVFD: A Versatile Online Fault Detection Scheme via Checking of Stability Violation”, IEEE Transactions on VLSI Systems, Vol.19, No.9, September 2011, pp.1627-1640 [9] Guihai Yan, Yinhe Han, Xiaowei Li, “ReviveNet: A Self-adaptive Architecture for Improving Lifetime Reliability via Localized Timing Adaptation”, IEEE Transactions on Computers, Volume 60, Issue 9, September 2011, pp.1219-1232 [10] Dongrui Fan, Xiaowei Li, Guojie Li, “New Methodologies for Parallel Architecture”, Journal of Computer Science and Technology, 26(4): 578-584, July 2011 [11] Guihai Yan, Yinhe Han, Hui Liu, Xiaoyao Liang, Xiaowei Li, “Microfix: Using timing interpolation and delay sensors for power reduction”, ACM Transactions on Design Automation of Electronic Systems, March 2011, Vol. 16, No. 2, Article 16:1-21 [12] Zhulin An, Hongsong Zhu, Chaonong Xu, Yongjun Xu, Xiaowei Li, “Synchronization of Linear Pulse-coupled Oscillators with Different Frequency”, IEEE Transactions on Industry Electronics, Vol.58, No.6, June 2011, pp. 2205-2215 [13] Yu Yang, Yongjun Xu, Xiaowei Li, “A Loss Inference Algorithm for Wireless Sensor Networks to Improve Data Reliability of Digital Ecosystems”, IEEE Transactions on Industry Electronics, Vol.58, No.6, June 2011, pp. 2126-2137 [14] Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li, “An Abacus Turn Model for Time/Space-Efficient Reconfigurable Routing”, Proc. of IEEE 38th International Symposium on Computer Architecture (ISCA), San Jose, USA, June 4-8, 2011, pp.259-270 [15] Jia Li, Qiang Xu, Yu Hu, and Xiaowei Li, “X-Filling for Simultaneous Shift- and Capture- Power Reduction in At-Speed Scan-Based Testing”, IEEE Transactions on VLSI Systems, Vol.18, No.7, July. 2010, pp.1081-1092 [16] Guihai Yan, Xiaoyao Liang, Yinhe Han, Xiaowei Li, “Leveraging the Core-Level Complementary Effects of PVT Variations to Reduce Timing Emergencies in Multi-Core Processors”, Proc. of IEEE 37th International Symposium on Computer Architecture (ISCA), Saint-Malo, France, June 19-23, 2010, pp.485-496 [17] Lei Zhang, Yinhe Han, Qiang Xu, Xiaowei Li, Huawei Li, “On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems”, IEEE Transactions on VLSI Systems, Vol.17, No.9, Sept. 2009, pp.1173-1186 [18] Yinhe Han, Yu Hu, Xiaowei Li, Anshuman Chandra, Huawei Li, “Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for System-on-a-Chip”, IEEE Transactions on VLSI Systems, Vol.15, No.5, May 2007, pp.531-540 [19] Yinhe Han, Xiaowei Li, Huawei Li, Anshuman Chandra, “Embedded Test Resource for SoC to Reduce Required Tester Channels Based on Advanced Convolutional Codes”, IEEE Transactions on Instrumentation and Measurement, Vol.55, No.2, April, 2006, pp.389-399 [20] Xiaowei Li, Ming Shao, Guanghui Li, “Formal Verification Techniques Based on Boolean Satisfiability Problem”, Journal of Computer Science and Technology, Vol.20, No.1, 2005, pp. 38-47
附件下载：
李晓维
科研人员近年来主要研究领域为VLSI测试、容错计算；在包括ISCA/HPCA/DSN/DAC/ICCAD等IEEE国际学术会议、IEEE/ACM Transactions等国际学术刊物、中国科学/JCST等国内学术刊物上合作发表学术论文300余篇；授权发明专利60余件、软件著作权登记40余项。先后获得中国科学院自然科学奖（1992年度）、杰出科技成就奖（团队/2003年度）、教学成果奖（2008年度）；获得中国计算机学会王选奖（2008年度）、中国质量学会质量技术奖（2011年度）；北京市科学技术奖（2007/2008/2014/2017年度）；国家技术发明奖（2012年度）；国家科技进步奖（2015年度）。
现任中国计算机学会监事长、曾任常务理事、容错计算专业委员会主任；Journal of Computer Science and Technology (JCST)副主编；Journal of Electronic Testing: Theory and Applications (JETTA) 和Journal of Low Power Electronics (JOLPE) 编委；IEEE Asia and Pacific Regional TTTC Vice-Chair；IEEE ATS Steering Committee Chair；担任IEEE VTS/DATE/PRDC/ASP-DAC等国际学术会议程序委员会委员。
代表论著
[1] 李晓维, 吕涛, 李华伟, 李光辉 著《数字集成电路设计验证——量化评估, 激励生成, 形式化验证》, 科学出版社, 2010年5月, 518千字, 411页
[2] 李晓维, 韩银和, 胡瑜, 李佳 著《数字集成电路测试优化——测试压缩, 测试功耗优化,测试调度》, 科学出版社, 2010年6月, 433千字, 344页
[3] 李晓维, 胡瑜, 张磊, 鄢贵海 著《数字集成电路容错设计——容缺陷/故障, 容参数偏差,容软错误》, 科学出版社, 2011年4月, 546千字, 433页
[4] Xiang Fu, Huawei Li, Xiaowei Li, “Testable Path Selection and Grouping for Faster Than At-Speed Testing”,IEEE Transactions on VLSI Systems, Vol.11, No.02, February 2012, pp.236-247
[5] Guihai Yan, Yingmin Li, Yinhe Han, Xiaowei Li, Xiaoyao Liang, “SAAS+RAAS: a Hybrid Application Scheduling Scheme using Mixed Voltage Regulators for DVFS in a Multicore Architecture”, IEEE The High-Performance Computer Architecture Symposium (HPCA-18), February 25-29, 2012, New Orleans, Louisiana, USA
[6] Minjin Zhang, Huawei Li, Xiaowei Li, “Path Delay Test Generation Toward Activation of Worst Case Coupling Effects”, IEEE Transactions on VLSI Systems, Vol.10, No.11, November 2011, pp.1969-1982
[7] Ying Zhang, Huawei Li, Yinhua Min, Xiaowei Li, “Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects”, IEEE Transactions on VLSI Systems, Vol.10, No.10, October 2011, pp.1787-1800
[8] Guihai Yan, Yinhe Han, Xiaowei Li, “SVFD: A Versatile Online Fault Detection Scheme via Checking of Stability Violation”, IEEE Transactions on VLSI Systems, Vol.19, No.9, September 2011, pp.1627-1640
[9] Guihai Yan, Yinhe Han, Xiaowei Li, “ReviveNet: A Self-adaptive Architecture for Improving Lifetime Reliability via Localized Timing Adaptation”, IEEE Transactions on Computers, Volume 60, Issue 9, September 2011, pp.1219-1232
[10] Dongrui Fan, Xiaowei Li, Guojie Li, “New Methodologies for Parallel Architecture”, Journal of Computer Science and Technology, 26(4): 578-584, July 2011
[11] Guihai Yan, Yinhe Han, Hui Liu, Xiaoyao Liang, Xiaowei Li, “Microfix: Using timing interpolation and delay sensors for power reduction”, ACM Transactions on Design Automation of Electronic Systems, March 2011, Vol. 16, No. 2, Article 16:1-21
[12] Zhulin An, Hongsong Zhu, Chaonong Xu, Yongjun Xu, Xiaowei Li, “Synchronization of Linear Pulse-coupled Oscillators with Different Frequency”, IEEE Transactions on Industry Electronics, Vol.58, No.6, June 2011, pp. 2205-2215
[13] Yu Yang, Yongjun Xu, Xiaowei Li, “A Loss Inference Algorithm for Wireless Sensor Networks to Improve Data Reliability of Digital Ecosystems”, IEEE Transactions on Industry Electronics, Vol.58, No.6, June 2011, pp. 2126-2137
[14] Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li, “An Abacus Turn Model for Time/Space-Efficient Reconfigurable Routing”, Proc. of IEEE 38th International Symposium on Computer Architecture (ISCA), San Jose, USA, June 4-8, 2011, pp.259-270
[15] Jia Li, Qiang Xu, Yu Hu, and Xiaowei Li, “X-Filling for Simultaneous Shift- and Capture- Power Reduction in At-Speed Scan-Based Testing”, IEEE Transactions on VLSI Systems, Vol.18, No.7, July. 2010, pp.1081-1092
[16] Guihai Yan, Xiaoyao Liang, Yinhe Han, Xiaowei Li, “Leveraging the Core-Level Complementary Effects of PVT Variations to Reduce Timing Emergencies in Multi-Core Processors”, Proc. of IEEE 37th International Symposium on Computer Architecture (ISCA), Saint-Malo, France, June 19-23, 2010, pp.485-496
[17] Lei Zhang, Yinhe Han, Qiang Xu, Xiaowei Li, Huawei Li, “On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems”, IEEE Transactions on VLSI Systems, Vol.17, No.9, Sept. 2009, pp.1173-1186
[18] Yinhe Han, Yu Hu, Xiaowei Li, Anshuman Chandra, Huawei Li, “Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for System-on-a-Chip”, IEEE Transactions on VLSI Systems, Vol.15, No.5, May 2007, pp.531-540
[19] Yinhe Han, Xiaowei Li, Huawei Li, Anshuman Chandra, “Embedded Test Resource for SoC to Reduce Required Tester Channels Based on Advanced Convolutional Codes”, IEEE Transactions on Instrumentation and Measurement, Vol.55, No.2, April, 2006, pp.389-399
[20] Xiaowei Li, Ming Shao, Guanghui Li, “Formal Verification Techniques Based on Boolean Satisfiability Problem”, Journal of Computer Science and Technology, Vol.20, No.1, 2005, pp. 38-47
科研项目
[1] 973课题“大规模高通量计算系统的可靠性设计”(2011CB302503)；405万
[2] 973课题“高性能处理芯片的可靠性设计”(2005CB321604)；500万
[3] NSFC重点项目“数字VLSI电路测试技术研究”(60633060)；200万
[4] NSFC重点项目“从行为级到版图级的设计验证与测试生成”(60207002)；200万
[5] NSFC项目“微处理器自修复设计基础技术研究”(90707004)；80万
[6] NSFC与RGC联合资助项目“片上系统测试架构设计与优化：针对噪声引起的测试良产率下降的研究”(60831160526)；31万
[7] 863项目“大规模高可靠片上多处理器的系统结构及实现方法”(2007AA01Z113)；89万
[8] 863项目“软硬件协同的低功耗系统设计”(2001AA111070)；50万
[9] 北京市科技重点课题“IC设计验证/测试关键技术研发与实用”(H020120140130)；400万
[10] XX预研项目“软件可靠性测试基础技术” (41315050102)；95万