[1]Jia Li, Qiang Xu, Yu Hu and Xiaowei Li, "On Improving Channel Utilization in Testing NoC-Based Systems", Informal Digest of Papers, IEEE European Test Symposium, May 2007, Germany, pp.53-58
[2]Yang Zhao, Tao Lv, Ling-yi Liu, Hua-wei Li, Xiao-wei Li, "A Novel Circuit-Oriented SAT Engine and Its Application to Unbounded Model Checking", Informal Digest of Papers, IEEE European Test Symposium, May 2007, Germany, pp.41-46
[3]Lei Zhang, Yinhe Han, Qiang Xu, Xiaowei Li, "Topology Reconfiguration Problem for Core-Level Redundancy in Homogeneous Chip Many-Core Processors", fast abstracts, 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07), June, 2006, UK
[4]Lei Zhang, Huawei Li, Xiaowei Li, "A Routing Algorithm for Random Error Tolerance in Network-on-chip", Proc. of 12th International Conference on Human-Computer Interaction (HCI'07), Beijing, July, 2007, pp.1210-1219
[5]Da Wang, Xiaoxin Fan, Xiang Fu, Hui Liu, Ke Wen, Peter Li, Huawei Li, Yu Hu, and Xiaowei Li'The Design-For-Testability Features of Godson-2 Microprocessor', Proc. of IEEE International Test Conference (ITC'07), Oct. 2007, USA
[6]Minjing Zhang, Huawei Li, Xiaowei Li, "Test Generation for Crosstalk Glitches Considering Multiple Coupling Effects", Proc. of IEEE Asian Test Symposium (ATS), Oct. 2007, Beijing, pp.259-264
[7]Shaohua Lei, Yinhe Han, Xiaowei Li, "a frequency analysis model for propagation of transient errors in combinational logic", Proc. of IEEE Asian Test Symposium (ATS), Oct. 2007, Beijing, pp.223-228
[8]Xiaoxin Fan, Yu Hu, Laung-Terng Wang, "An On-Chip Test Contrl Scheme for Multi-Clock At-Speed Testing", Proc. of IEEE Asian Test Symposium (ATS), Oct. 2007, Beijing, pp.341-348
[9]Tal Lv, Yang Zhao, Huawei Li, Xiaowei Li, "Design Verification of an Embedded Processor: From Error Model to Test Method", Digest of Papers, IEEE 8th Workshop on RTL and High-Level Testing (WRTLT'07), October 12-13, Beijing, pp.25-30
[10]Fei Wang, Yu Hu, Xiaowei Li, "A Design-for-Diagnosis Technique for diagnosing Integrated Circuit Faults with Faulty Scan Chains", Digest of Papers, IEEE 8th Workshop on RTL and High-Level Testing (WRTLT'07), October 12-13, Beijing, pp.51-59
[11]Guihai Yan, Yinhe Han, Xiaowei Li, Hui Liu, "Performance-Driven Crosstalk Mitigation Based on Bus-Grouping Transmission", Digest of Papers, IEEE 8th Workshop on RTL and High-Level Testing (WRTLT'07), October 12-13, Beijing, pp.119-124
[12]Ying Zhang, Huawei Li, Xiaowei Li, "MT Comtacted Set for Interconnect Crosstalk on SOC", Digest of Papers, IEEE 8th Workshop on RTL and High-Level Testing (WRTLT'07), October 12-13, Beijing, pp.125-130
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