Dr. Laung-Terng (L.-T.) Wang (from SynTest) gave a talk

On November 19, 2009, Dr. Laung-Terng (L.-T.) Wang, Chairman and CEO, SynTest Technologies, Sunnyvale, CA, visited our lab. and gave a talk, entitled "CSER: Concurrent Soft-Error Resilience".

Abstract: In recent years, developing robust soft-error detection and correction circuits for protecting chips against single-event upsets (SEUs) has drawn a lot of attention. These robust circuits center on using the hardening or the built-in soft error resilience (BISER) technique to mitigate SEUs that may arise from sequential elements. In this talk, Dr. Wang will present a patent-pending concurrent soft-error resilience(CSER) scheme, based on the BISER technique, additional manufacturing test, online debug, and defect tolerance capabilities. Using the proposed CSER scheme, the BISER cells are reconfigured as robust CSER cells for slow-speed snapshot, slow-speed signature analysis, and defect tolerance. Dr. Wang will compare the impact of these robust CSER cells with the BISER cells on cell-level overhead in area , power, and performance, to demonstrate the effectiveness of the proposed scheme.

Bio: Laung-Terng (L.-T.) Wang, chairman and chief executive officer (CEO) of SynTest  Technologies(Sunnyvale, CA), is also a visiting professor in the Department of Electrical Engineering at National Taiwan University. He received his BSEE and MSEE degrees from National Taiwan University in1975 and 1977, respectively, and his MSEE and EE PhD degrees from Stanford University in 1982 and 1987, respectively. 
Dr. Wang founded SynTest Technologies in 1990. The design-for-testability (DFT) technologies Dr. Wang has developed have been successfully implemented in thousands of ASIC designs worldwide. He currently holds 21 U.S. Patents, 15 European Patents and one China Patent in the areas of scan synthesis, test generation, at-speed scan testing, test compression, logic built-in self-test (BIST), and design for debug-and-diagnosis (DFD). He has also co-authored and co-edited three internationally used DFT/EDA textbooks – VLSI Test Principles and Architectures (2006), System-on-Chip Test Architectures (2007), and Electronic Design Automation (2009) – with sales over 5,000 copies. 
As a member of Sigma Xi, Dr. Wang received a 2007 Meritorious Service Award from the IEEE Computer Society and he is a co-recipient of the 2009 IEICE Information and Systems Society Excellent Paper Award for an excellent series of papers that appeared in IEICE Transactions on Information and Systems during a period of five years. He is a Fellow of the IEEE and a Golden Core Member of the IEEE Computer Society.