Dr. Wenjing Rao (from Univ. of Illinois at Chicago) gave a talk

On July 9, 2008, Dr. Wenjing Rao (from University of Illinois at Chicago) visited our lab. and gave a talk entitled "Defect and Fault Tolerance for Nanoelectronic Systems".

Abstract: Reliability has been identified as a fundamental and severe challenge for the emerging nanoelectronic systems. As a result, both defect and fault tolerance become highly important to guarantee the basic requirement of computational correctness. Building reliable nanoelectronic systems requires considerations on: 1) high fault rate, 2) regular structured topology, and 3) strictly localized interconnect. In this talk, I will present two ongoing research directions towards the reliability issue of the future nanoelectronic systems. 
The reconfigurability of nano devices and the regular structure of nano fabrics make reconfiguration based repair an essential approach for both defect and fault tolerance. Ideally, repair based approaches have the best hardware efficiency when full sharing of redundancy is achievable. However, nanoelectronic systems are subject to strict constraints on localized interconnections, which limit the sharing of redundant resources to within a small neighborhood. To more fully understand this challenge, we provide a model for the issue of redundant resource sharing under locality constraint. We provide the associated algorithms for both defect and fault tolerance approaches on various system models. The proposed model and algorithms are applicable to any specific topology or layout of a nanoelectronic system, and can serves as a basis to formulate both the defect and fault tolerance problems under locality constraints.
In the second part, we focus on the defect / fault tolerance in nanoelectronic programmable logic arrays (PLAs), which, supported by the nano crossbar architectures, have been shown as promising as platforms for nanoelectronic logic.  However, the massive defects in the fabric impose strict constraints to the function mapping process. Therefore, the process of function mapping, which used to be a trivial phase in the logic design process, emerges as a new challenge. We establish the associated mathematic model for such a problem, and propose an algorithm to address the new challenge in synthesizing nanoelectronic two-level logic functions.

Short Bio:
BS: Peking University, Beijing
PhD: University of California, San Diego
Currently, assistant professor at University of Illinois at Chicago, ECE department