Publications

WARNING: Most of the papers are copyrighted by ACM or IEEE. You may browse the articles at your convenience, in the same spirit as you may read a journal or a proceedings article in a public library. They are posted here for your personal use, to ensure timely dissemination of research work with no commercial purpose.
In computer application and engineer areas, conference is same important as journal. We list the conference first because they represent our newest research achievements.

1. Referred Conference Papers

2017
[C54]Cheng Wang, Ying Wang, Yinhe Han, Lili Song, Zhenyu Quan, Jiajun Li, Xiaowei Li: CNN-based object detection solutions for embedded heterogeneous multicore SoCs. ASP-DAC 2017: 105-110
[C53]Xin He, Guihai Yan, Faqiang Sun, Yinhe Han, Xiaowei Li: ApproxEye: Enabling approximate computation reuse for microrobotic computer vision. ASP-DAC 2017: 402-407
[C52]Shiqi Lian, Ying Wang, Yinhe Han, Xiaowei Li: BoDNoC: Providing bandwidth-on-demand interconnection for multi-granularity memory systems. ASP-DAC 2017: 738-743
[C51]Shiqi Lian, Yinhe Han, Ying Wang, Yungang Bao, Hang Xiao, Xiaowei Li, Ninghui Sun: Dadu: Accelerating Inverse Kinematics for High-DOF Robots. DAC 2017: 59:1-59:6
[C50]Wenyan Lu, Guihai Yan, Jiajun Li, Shijun Gong, Yinhe Han, Xiaowei Li: FlexFlow: A Flexible Dataflow Accelerator Architecture for Convolutional Neural Networks. HPCA 2017: 553-564
2016
[C49]Xin He, Guihai Yan, Yinhe Han, Xiaowei Li: ACR: Enabling computation reuse for approximate computing. ASP-DAC 2016: 643-648
[C48]Ying Wang, Yinhe Han, Jun Zhou, Huawei Li, Xiaowei Li: DISCO: a low overhead in-network data compressor for energy-efficient chip multi-processors. DAC 2016: 37:1-37:6
[C47]Ying Wang, Jie Xu, Yinhe Han, Huawei Li, Xiaowei Li: DeepBurning: automatic generation of FPGA-based learning accelerators for the neural network family. DAC 2016: 110:1-110:6
[C46]Lili Song, Ying Wang, Yinhe Han, Xin Zhao, Bosheng Liu, Xiaowei Li: C-brain: a deep learning accelerator that tames the diversity of CNNs through adaptive data-level parallelization. DAC 2016: 123:1-123:6
2015
[C45]Hang Lu, Guihai Yan, Yinhe Han, Ying Wang, Xiaowei Li: ShuttleNoC: Boosting on-chip communication efficiency by enabling localized power adaptation. ASP-DAC 2015: 142-147
[C44]ing Wang, Yinhe Han, Cheng Wang, Huawei Li, Xiaowei Li: RADAR: a case for retention-aware DRAM assembly and repair in future FGR DRAM memory. DAC 2015: 19:1-19:6
[C43]Ying Wang, Yinhe Han, Lei Zhang, Huawei Li, Xiaowei Li: ProPRAM: exploiting the transparent logic resources in non-volatile memory for near data computing. DAC 2015: 47:1-47:6
[C42]Ying Wang, Lili Song, Yinhe Han, Yuanqing Cheng, Huawei Li, Xiaowei Li: A case of precision-tunable STT-RAM memory design for approximate neural network. ISCAS 2015: 1534-1537
[C41]Song Jin, Songwei Pei, Yinhe Han, Huawei Li: On optimizing system energy of multi-core SoCs based on dynamically reconfigurable voltage-frequency island. VLSI-DAT 2015: 1-4
2014
[C40]Yinhe Han, Ying Wang, Huawei Li, Xiaowei Li, "Data-aware DRAM refresh to squeeze the margin of retention time in hybrid memory cube", Proc. of ICCAD, pp. 295-300, 2014.
[C39]Xin He, Guihai Yan, Yinhe Han, Xiaowei Li,"SuperRange: Wide operational range power delivery design for both STV and NTV computing", Proc. of DATE, pp. 1-6,  2014.
[C38]Song Jin, Yinhe Han, Songwei Pei, "Variation-aware statistical energy optimization on voltage-frequency island based MPSoCs under performance yield constraints", Proc. of ASP-DAC,  pp. 720-725, 2014.  
[C37]Jun Ma, Guihai Yan, Yinhe Han, Xiaowei Li, "Amphisbaena: Modeling two orthogonal ways to hunt on heterogeneous many-cores", Proc. of ASP-DAC,  394-399, 2014.
2013
[C36]Yinhe Han, Ying Wang, Huawei Li, Xiaowei Li, "Enabling Near-Threshold Voltage(NTV) operation in Multi-VDD cache for power reduction",  Proc. of ISCAS, pp. 337-340, 2013.
[C35]Yinhe Han, Song Jin, Jibing Qiu, Qiang Xu, Xiaowei Li, “On predicting NBTI-induced circuit aging by isolating leakage change“, Proc. of ISQED 2013: 46-52, 2013. (PDF)
[C34]Hang Lu, Guihai Yan, Yinhe Han, Binzhang Fu, Xiaowei Li, “RISO: Relaxed Network-on-Chip Isolation for Cloud Processors”, Proc. of Design Automation Conference (DAC), 2013. (PDF)
[C33]Xueliang Li, Guihai Yan, Yinhe Han, Xiaowei Li, "SmartCap: user experience-oriented power adaptation for smartphone's application processor", Proc. of  DATE, pp. 57-60, 2013.
2012
[C32] Guihai Yan, Yingmin Li, Yinhe Han, Xiaowei Li, Minyi Guo, Xiaoyao Liang, "AgileRegulator: A Hybird Voltage Regulator Scheme Redeeming Dark Silicon for Power Efficiency in a Multicore Architecture", Proc. of High Performance Computer Architecture(HPCA), 2012. (PDF)
2011
[C31] Binzhang Fu, Yinhe Han, Jun Ma, Huawei Li, Xiaowei Li, "An Abacus Turn Model for Time/Space-Efficient Reconfigurable Routing", Proc. of IEEE/ACM International Symposium on Computer Architecture (ISCA), 2011. (PDF)
[C30] Jianbo Dong, Lei Zhang, Yinhe Han, Xiaowei Li, “Wear Rate Leveling: Lifetime Enhancement of PRAM with Endurance Variation”, Proc. of IEEE/ACM Design Automation Conference (DAC), 2011.(PDF)
[C29] Jianliang Gao, Yinhe Han, Xiaowei Li, “Avoiding Data Repetition and Data Loss in Debugging Multiple-Clock Chips”, Will appear in Proc. of IEEE/ACM Design, Automation, and Test in Europe (DATE), 2011.(PDF)
[C28] Ying Wang, Lei Zhang, Yinhe Han, Huawei Li and Xiaowei Li, “Smart Memory: exploiting and managing abundant off-chip optical bandwidth”, Will appear in Proc. of IEEE/ACM Design, Automation, and Test in Europe (DATE), 2011. (PDF)
[C27] Cheng Liu, Lei Zhang, Yinhe Han, Xiaowei Li, “Vertical Interconnects Squeezing in Symmetric 3D Mesh Network-on-Chip”, Will appear in Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC), 2011.(PDF)
[C26] Cheng Liu, Lei Zhang, Yinhe Han, Xiaowei Li, “A Resilient On-chip Router Design Through Data Path Salvaging”, Will appear in Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC), 2011.(PDF)
2010
[C25] Huawei Li, Dawen Xu, Yinhe Han, Kwang-Ting Cheng and Xiaowei Li, “nGFSIM : A GPU-Based Fault Simulator for 1-to-n Detection and its Applications”, Proc. of IEEE International Test Conference (ITC), paper 12.1, Nov. 2010.(PDF)
[C24]Song Jin, Yinhe Han, Huawei Li and Xiaowei Li, “P2CLRAF: An Pre- and Post-silicon Cooperated Circuit Lifetime Reliability Analysis Framework”, Proc. of IEEE Asian Test Symposium (ATS), 2010. (PDF)
[C23]Ying Wang, Lei Zhang, Yinhe Han, Huawei Li and Xiaowei Li, “Address Remapping for Static NUCA in NoC-based Degradable Chip-Multiprocessors”, Proc. of IEEE Pacific Rim International Symposium on Dependable
Computing (PRDC), 2010.
(PDF)
[C22] Guihai Yan, Xiaoyao Liang, Yinhe Han,  Xiaowei Li , “Leveraging the Core-Level Complementary Effects of PVT Variations to Reduce Timing Emergencies in Multi-Core Processors”, Proc. of IEEE/ACM International Symposium on Computer Architecture (ISCA), 2010. (PDF)
[C21] Bingzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li , “Binary-Tree Waveguide Connected Time/Power Efficient Optical Network-on-Chip”, Proc. of IEEE/ACM Design, Automation, and Test in Europe (DATE), 2010. (PDF)
[C20] Lei Zhang, Yu Yue, Yinhe Han, Xiaowei Li, Shangping Ren ,”Performance-Asymmetry-Aware Topology Virtualization for Defect-tolerant NoC-Based Many-core Processors”, Proc. of IEEE/ACM Design, Automation, and Test in Europe (DATE), 2010.(PDF)
2009
[C19] Jun Liu, Yinhe Han, Xiaowei Li , “Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power”, Proc. of IEEE Asian Test Symposium (ATS), 2009.
[C18] Song Jin, Yinhe Han, Lei Zhang, Huawei Li , Xiaowei Li and Guihai Yan,” M-IVC: Using Multiple Input Vectors to Minimize Aging-induced Delay”, Proc. of IEEE Asian Test Symposium (ATS), 2009.(PDF)
[C17] Jianbo Dong, Lei zhang, Yinhe Han, Guihai Yan and Xiaowei Li , “Variation-Aware Scheduling for Chip Multiprocessors with Thread Level Redundancy”, Proc. of IEEE Pacific Rim International Symposium on Dependable Computing (PRDC), 2009.(PDF)
[C16] Bingzhang Fu, Yinhe Han, Huawei Li and Xiaowei Li ,”A New Multiple-Round DOR Routing for 2D Network-on-chip Meshes”,Proc. of IEEE Pacific Rim International Symposium on Dependable Computing (PRDC), 2009.(PDF)
[C15] Guihai Yan, Yinhe Han, Hui Liu, Xiaoyao Liang, Xiaowei Li, "MicroFix: Exploiting Path-grained Timing Adaptability for Improving Power-Performance Efficiency", International Symposium on Low Power Electronics and Design(ISLPED), 2009.(PDF)
[C14] Guihai Yan, Yinhe Han, Xiaowei Li, “A Unified Online Fault Detection Scheme via Checking of Stability Violation”,  Design, Automation and Test in Europe 2009. (PDF)
[C13] Jianliang Gao, Yinhe Han, and Xiaowei Li, "A New Post-silicon Debug Approach Based on Suspect Window",  VLSI Test Symposium(VTS), 2009. (PDF)
2008
[C12] Lei Zhang, Yinhe Han, Qiang Xu, and Xiaowei Li, “Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology,” IEEE/ACM Design, Automation and Test in Europe (DATE), pp. 891-896, 2008. (PDF)
2007
[C11] Lei Zhang, Yinhe Han, Qiang Xu, and Xiaowei Li, “Topology Reconfiguration Problem for Core-Level Redundancy in Homogeneous Chip Many-core Processors,” Fast Abstract, IEEE/IFIP International Conference on Dependable System and Networks (DSN), pp. 364-365, 2007. (PDF)
[C10] Shaohua Lei, Yinhe Han, Xiaowei Li, "Frequency Analysis Model for Propagation of Transient Errors in Combinational Logic", Proc. of IEEE Asian Test Symposium (ATS), Oct. 2007, Beijing, pp.223-228. (PDF)
2006
[C9] Tong Liu, Huawei Li, Xiaowei Li, and Yinhe Han, “Fast Packet Classification using Group Bit Vector”, Proc. of 49th Annual IEEE Global Telecommunications Conference (Globecom2006), pp.1-5, 2006. (PDF)
[C8]Jie Dong, Yu Hu, Yinhe Han, Xiaowei Li, “An On-chip Combinational Decompressor for Reducing Test Data Volume”, Proc. of IEEE International Symposium on Circuits and Systems (ISCAS'06), May 21-24, 2006, Greece, pp.1459-1462
2005
[C7] Yinhe Han, Yu Hu, Xiaowei Li, and Huawei Li, “Using MUXs Network to Hide Bunches of Scan Chains,” in Proc. IEEE/ACM International Symposium on Quality Electronic Design (ISQED), pp. 238-243, May 2005. (PDF)
[C6] Yinhe Han, Yu Hu, Huawei Li, and Xiaowei Li, “Theoretic Analysis and Enhanced X-Tolerance of Test Response Compact based on Convolutional code,” in Proc. IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), pp. 53-58, January 2005. (PDF)
[C5] Ji Li, Yinhe Han, Xiaowei Li, “Deterministic and Low Power BIST Based on Scan Slice Overlapping”, Proc. of IEEE of International Symposium on Circuits and Systems (ISCAS), May 2005, Kobe, Japan, pp.5670-5673. (PDF)
2004
[C4] Yinhe Han, Yu Hu, Anshuman Chandra, Huawei Li, and Xiaowei Li, “Rapid and Energy-Efficient testing for Embedded Cores,” in Proc. IEEE Asian Test Symposium, pp. 8-13, November 2004. (EI Access: 05078836557) (PDF)
[C3] Yinhe Han, Yongjun Xu, Huawei Li, Xiaowei Li, and Anshuman Chandra, “Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes,” in Proc. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 298-305, Cannes, France, October 2004.(EI Access: 05399379765) (PDF)
[C2] Yu Hu, Yinhe Han, Huawei Li, Tao Lv, Xiaowei Li, “Pair Balance-Based Test Scheduling for SOCs”, Proc. of IEEE 13th Asian Test Symposium (ATS'04) , Kenting, November 15-17, 2004, pp.236-241. (PDF)
2003
[C1] Yinhe Han, Yongjun Xu, Anshuman Chandra, Huawei Li, and Xiaowei Li, “Test Resource Partitioning Based on Efficient Response Compaction for Test TArime and Tester Channel Reduction,” in Proc. IEEE Asian Test Symposium, pp. 440-445, November 2003. (PDF)

2. Journals

2017
[J38] Ying Wang, Yinhe Han, Cheng Wang, Huawei Li, Xiaowei Li: Retention-Aware DRAM Assembly and Repair for Future FGR Memories. IEEE Trans. on CAD of Integrated Circuits and Systems 36(5): 705-718 (2017)
[J37] Lili Song, Ying Wang, Yinhe Han, Huawei Li, Yuanqing Cheng, Xiaowei Li: STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator. IEEE Trans. VLSI Syst. 25(4): 1285-1296 (2017)
20166
[J36] Xin He, Guihai Yan, Yinhe Han, Xiao-Wei Li: Wide Operational Range Processor Power Delivery Design for Both Super-Threshold Voltage and Near-Threshold Voltage Computing. J. Comput. Sci. Technol. 31(2): 253-266 (2016)
[J35] Song Jin, Yinhe Han, Songwei Pei: Statistical energy optimization on voltage-frequency island based MPSoCs in the presence of process variations. Microelectronics Journal 54: 23-31 (2016)
[J34] Jun Ma, Guihai Yan, Yinhe Han, Xiaowei Li: An Analytical Framework for Estimating Scale-Out and Scale-Up Power Efficiency of Heterogeneous Manycores. IEEE Trans. Computers 65(2): 367-381 (2016)
[J33] Song Jin, Songwei Pei, Yinhe Han, Huawei Li: A Cost-Effective Energy Optimization Framework of Multicore SoCs Based on Dynamically Reconfigurable Voltage-Frequency Islands. ACM Trans. Design Autom. Electr. Syst. 21(2): 27 (2016)
[J32] Guihai Yan, Jun Ma, Yinhe Han, Xiaowei Li: EcoUp: Towards Economical Datacenter Upgrading. IEEE Trans. Parallel Distrib. Syst. 27(7): 1968-1981 (2016)
[J31] Yinhe Han, Jianbo Dong, Kaiheng Weng, Ying Wang, Xiaowei Li: Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation. IEEE Trans. VLSI Syst. 24(1): 92-102 (2016)
[J30]Ying Wang, Yinhe Han, Huawei Li, Xiaowei Li: VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache. IEEE Trans. VLSI Syst. 24(3): 858-870 (2016))
[J29]Ying Wang, Yinhe Han, Huawei Li, Lei Zhang, Yuanqing Cheng, Xiaowei Li: PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM. IEEE Trans. VLSI Syst. 24(5): 1613-1625 (2016)
2015
[J28]Bosheng Liu, Ying Wang, Zhiqiang You, Yinhe Han, Xiaowei Li: A signal degradation reduction method for memristor ratioed logic (MRL) gates. IEICE Electronic Express 12(8): 20150062 (2015)
[J27]Ying Wang, Yinhe Han, Lei Zhang, Binzhang Fu, Cheng Liu, Huawei Li, Xiaowei Li: Economizing TSV Resources in 3-D Network-on-Chip Design. IEEE Trans. VLSI Syst. 23(3): 493-506 (2015)
[J26]Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li: Data Remapping for Static NUCA in Degradable Chip Multiprocessors. IEEE Trans. VLSI Syst. 23(5): 879-892 (2015)
[J25]Hang Lu, Binzhang Fu, Ying Wang, Yinhe Han, Guihai Yan, Xiaowei Li: RISO: Enforce Noninterfered Performance With Relaxed Network-on-Chip Isolation in Many-Core Cloud Processors. IEEE Trans. VLSI Syst. 23(12): 3053-3064 (2015)
[J24]Ying Wang, Yinhe Han, Lei Zhang, Binzhang Fu, Cheng Liu, Huawei Li, Xiaowei Li, "Economizing TSV Resources in 3-D Network-on-Chip Design",  IEEE Trans. VLSI Syst. 23(3), pp. 493-506, 2015.
2014
[J33]Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li, "ZoneDefense: A Fault-Tolerant Routing for 2-D Meshes Without Virtual Channels",  IEEE Trans. VLSI Syst,  22(1), pp. 113-126, 2014.
[J32]Dawen Xu, Huawei Li, Amirali Ghofrani, Kwang-Ting Cheng, Yinhe Han, Xiaowei Li, "Test-Quality Optimization for Variable $n$ -Detections of Transition Faults", IEEE Trans. VLSI Syst, 22(8), pp. 1738-1749, 2014.
[J31]Xueliang Li, Guihai Yan, Yinhe Han, Xiaowei Li, "SmartCap: Using Machine Learning for Power Adaptation of Smartphone's Application Processor", ACM Trans. Design Autom. Electr. Syst, 20(1), 8 , 2014.
[J30]Peng Chen, Lei Zhang, Yinhe Han, Yunji Chen, "A General-Purpose Many-Accelerator Architecture Based on Dataflow Graph Clustering of Applications", J. Comput. Sci. Technol, 29(2), pp. 239-246, 2014.
[J29] Ying Wang, Lei Zang, Yinhe Han, Huawei Li, "Reinventing Memory System Design for Many-Accelerator Architecture", J. Comput. Sci. Technol, 29(2), pp. 273-280, 2014.
2013
[J28]Yinhe Han, Cheng Liu, Hang Lu, Wenbo Li, Lei Zhang, Xiaowei Li, "RevivePath: Resilient Network-on-Chip Design Through Data Path Salvaging of Router", J. Comput. Sci. Technol, 28(6), pp.1045-1053 , 2013.
[J27] Yuanqing Cheng, Lei Zhang, Yinhe Han, Xiaowei Li, "TSV Minimization for Circuit - Partitioned 3D SoC Test Wrapper Design",  J. Comput. Sci. Technol, 28(1), pp. 119-128, 2013.
[J26]Yuanqing Cheng, Lei Zhang, Yinhe Han, Xiaowei Li, "Thermal-Constrained Task Allocation for Interconnect Energy Reduction in 3-D Homogeneous MPSoCs", IEEE Trans. VLSI Syst, 21(2), pp. 239-249, 2013.
[J25] Song Jin, Yinhe Han, Huawei Li, Xiaowei Li, "Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction", IEEE Trans. VLSI Syst, 21(5), pp. 821-833, 2013.
2012
[J24]Song Jin, Yinhe Han, "M-IVC: Applying multiple input vectors to co-optimize aging and leakage", Microelectronics Journal, 43(11), pp. 838-847, 2012.
[J23]Yuanqing Cheng, Lei Zhang, Yinhe Han, Xiaowei Li, "Thermal-Constrained Task Allocation for Interconnect Energy Reduction in 3-D Homogeneous MPSoCs", IEEE Transactions on Very Large Scale Integration(VLSI) Systems, 2012. 
2011
[J22] Guihai Yan, Yinhe Han, Hui Liu, Xiaoyao Liang, Xiaowei Li, "MicroFix: Using Timing Interpolation and Delay Sensors for Power Reduction", ACM Transactions on Design Automation of Electronic Systems, 16(2), Artical 16, 2011.  (PDF)
[J21] Guihai Yan, Yinhe Han, Xiaowei Li, "ReviveNet: A Self-Adaptive Architecture for Improving Lifetime Reliability via Localized Timing Adaptation", IEEE Transactions on Computers, 60(9), pp. 1219-1231, 2011.  (PDF)
2010
[J20]Jianbo Dong, Lei Zhang, Yinhe Han, Guihai Yan and Xiaowei Li, “Performance-asymmetry-aware scheduling for Chip Multiprocessors with static core coupling”, Journal of Systems Architecture, 56, 534-542, 2010.
[J19] Jianliang Gao, Yinhe Han, Xiaowei Li, “A Novel Post-Silicon Debug Mechanism Based on Suspect Window”, IEICE Transactions on Information and Systems, Vol.E93-D  No.5  pp.1175-1185, 2010.
[J18] Jun Liu, Yinhe Han, Xiaowei Li, “Extended Selective Encoding for Reducing Test Data and Test Power”, IEICE Transactions on Information and Systems ,Vol.E93-D No.8,  pp.2223-2232,2010.
2009
[J17] Lei Zhang, Yinhe Han, Qiang Xu, Xiaowei Li and Huawei Li. “On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems”,  IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.17, pp.1173-1186, 2009. (PDF)
[J16] Wei Wang, Yin-He Han, Xiao-Wei Li, Fang Fang. “Co-optimization of Dynamic/Static Test Power in Scan Test”,   Chinese Journal of Electronics. (PDF)
2008
[J15] Guihai Yan, Yinhe Han, Xiaowei Li, and Hui Liu, “BAT: Performance-Driven Crosstalk Mitigation Based on Bus-grouping Asynchronous Transmission,” IEICE Transactions on Electronic,E91-C(10), pp. 1690-1697, 2008. (PDF)
2007
[J14] Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, and Anshuman Chandra, “Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit,” IEEE Transactions on Very Large Scale Integration Systems, Vol. 15, No. 5, pp. 531-540, May 2007. (PDF)
[J13] Wang Wei,  Hu Yu,  Han Yinhe,  Li Xiaowei, Zhang Yousheng,“Leakage Current Optimization Techniques during Test based on Don’t Care Bits Assignment,”Journal of Computer Science and Technology, Vol. 22, No. 5, pp. 673-680, 2007. (PDF)
[J12] Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li, "A Fault Tolerance Mechanism in Chip Many-core Processors", Tsinghua Science and Technology, Vol.12, No.S1, July 2007, pp.169-174. (PDF)
2006
[J11] Yinhe Han, Xiaowei Li,  Huawei Li, and Anshuman Chandra, “Embedded Test Resource for SoC to Reduce Required Tester Channels Based on Advanced Convolutional Codes,” IEEE Transactions on Instrumentation and Measurement, Vol. 55, No. 2, pp. 389-399, April 2006. (SCI IDS: 026IB, EI Access: 06149794655) (PDF)
[J10] Yinhe Han, Huawei Li, Xiaowei Li, and Anshuman Chandra, “Response Compaction for Test Time and Required TAM Width Reduction Based on Advanced Convolutional Codes,” Science In China: Serial F, Vol. 49, No.2, pp. 262-272, April 2006. (PDF)
[J9] Yu Hu, Yinhe Han, Xiao Li, Huawei Li, and Xiaoqing Wen, “Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time Received,” IEICE Transactions on Information and Systems, Vol. E89-D,  No. 10, pp.2616-2625, Oct. 2006. (PDF)
[J8] Wei Wang, Yinhe Han, Xiaowei Li, Yousheng Zhang, "Techniques of Leakage Current Optimization Based on Don't Care Bits in Test Vectors ", ACTA Electronica Sinica, Vol. 34, No. 2, pp.282-286, 2006. (in Chinese)
[J7] Jie Dong, Yu Hu, Yinhe Han, Xiaowei Li, "A Multiple-Scan-Chain Test Approach Based on Combinational Decompression Circuits ", JournalL of Computer Research and Development, Vol. 43, No. 6, pp.1001-1007, 2006. (in Chinese)
[J6] Yu Hu, Yinhe Han, Xiaowei Li, "Design-for-Testability and Test Technologies for System-on-a-Chip ", Journal of Computer Research and Development, Vol. 42, No. 1, pp.153-162, 2006. (in Chinese)
2005
[J5] Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, Anshuman Chandra, and Xiaoqing Wen, “Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores,” IEICE Transactions On Information and Systems, Vol. E88-D, No.9, pp. 2126-2134, Sept. 2005. (SCI IDS: 967HJ, EI Access: 05429418698). (PDF)
[J4] Yinhe Han, Yongjun Xu, Anshuman Chandra, Huawei Li, and Xiaowei Li, “Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction,” Journal of Computing Science and Technology (JCST), pp. 201-210,20(2), Feb. 2005. (SCI IDS: 910GN,EI Access: 05209106292) (PDF)
[J3] Yongjun Xu, Yinhe Han, Huawei Li, Xiaowei Li, "Power Sensitivity Analysis of Combinational Circuits Using Statistical Method ", Journal of Computer-Aided Design & Computer Graphics, Vol. 17, No. 1, pp.122-128, 2005. (in Chinese)
2004
[J2] Yinhe Han, Xiaowei Li, Yongjun Xu, Huawei Li, "Test Resource Partitioning Using Variable-Tail Code ", ACTA Electronica Sinica, Vol. 32, No. 8, pp.1346-1350, 2004. (in Chinese)
[J1] Yongjun Xu, Yinhe Han, Zuying Luo, Xiaowei Li, "Maximum Power-up Current Estimation Based on Genetic Algorithm ", Chinese Journal of Computers, Vol. 27, No. 2, pp.186-191, 2004. (in Chinese)

3. Workshop Presentations

2009
[W7]Dawen Xu,Yinhe Han Huawei Li and Xiaowei Li, ,"A Fast and Memory-Efficient Fault Simulation Using GPU", IEEE 10th Workshop on RTL and High Level Testing, 2009.
[W6] Song Jin,Lei Zhang, Huawei Li and Xiaowei Li, “On Predicting the Maximum Circuit Aging”, IEEE 10th Workshop on RTL and High Level Testing, 2010.
[W5] Jun Liu, Yinhe Han,Xiaowei Li ,"Scan Slices Compression Technique Using Dynamical Updating Reference Slices",  IEEE 10th Workshop on RTL and High Level Testing, 2009.
2008
[W4] Yinhe Han, Fang Fang, Wei Wang, Jianbo Dong, Xiaowei Li, Shanlin Yang, “Multicast Testing Method for NoC-based SoC Using Test Branches” IEEE 9th Workshop on RTL and High Level Testing, pp. 1-6, 2008. (PDF)
[W3] Binzhang Fu, Yinhe Han, Huawei Li and Xiaowei Li, “A New Methodology of reusing Network-on-Chip as Test-Access-Mechanism,” 2nd Workshop on Diagnostic Services in Network-on-Chips, pp.245-278, 2008. (PDF)
2007
[W2] Guihai Yan, Yinhe Han, Xiaowei Li, Hui Liu, "Performance-Driven Crosstalk Mitigation Based on Bus-Grouping Transmission", Digest of Papers, IEEE 8th Workshop on RTL and High-Level Testing (WRTLT'07), October 12-13, Beijing, pp.119-124. (PDF)
2006
[W1] Wei Wang, Yinhe Han, Xiaowei Li, Yousheng Zhang, Yu Hu and Huawei Li, “PowerCut- A Novel Low-power scan testing”, Digest of Papers, IEEE 7th Workshop on RTL and High-Level Testing (WRTLT’06), July 23-24, 2006, Fukuoka, Japan, pp.49-54. (PDF)

4. Patents (granted)

2007

[P5] Yinhe Han and Xiaowei Li, “A Quick Test Flow Optimization Technique”. Chinese Patent Number: ZL20041000672.7, Date of Patent: Jul. 8, 2007.

[P4] Yinhe Han and Xiaowei Li, “A Parallel Wrapper Design Circuit for System-On-a-Chip” . Chinese Patent Number: ZL200410047572.1, Date of Patent: Jun. 27, 2007.

[P3] Yinhe Han and Xiaowei Li, “On-Chip Quick Signal Generation Circuit for AC Scan Test”. Chinese Patent Number: ZL200410004831.2, Date of Patent: Mar. 5, 2007.

[P2] Yinhe Han and Xiaowei Li, “A Coding Method of Advanced Convolutional Code” . Chinese Patent Number: ZL200410045981.8, Date of Patent: Feb. 6, 2007.

2006

[P1] Yinhe Han and Xiaowei Li, “A Free-Feedback Sequential Response Compactor with Single Output” . Chinese Patent Number: ZL03149074.3, Date of Patent: Sept. 27, 2006.

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