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  Yinhe HAN (韩银和)
Professor
Chair of Young Computer Scientists & Engineers Forum(YOCSEF), China Computer Federation(CCF),2016-2017
Key Laboratory of Computer System and Architecture,
Institute of Computing Technology, Chinese Academy of Sciences
Email:  , Office Tel: (86)10-6260-0717
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Recent News:
  • We win the 2016 Design Automation Conference(DAC) Low-Power Image Recognition Challenge(LPIRC) (2016-6)
  • Prof. Sharon Hu and Ziyi Chen from University of Notre Dame visited our group and gave a talk (2016-6)
  • Yinhe Han is supported by NSFC for Outstanding Young Scholars(2015-9).
  • Prof. Per Stenstrom from Chalmers University of Technology visited our group and gave a talk. (2014-10)
  • Prof. Sandip kundu from University of Massachusetts visited our group and gave a talk. (2014-4)
  • Prof. Subhasish Mitra from Stanford University visited our group and gave a talk. (2013-9)
  • Prof. David Brooks from Harvard University visited our group and gave a talk.(2013-9)
  • Prof. Dean Tullsen from UCSD visited our group and gave a talk(2013-8)
  • Prof. Tim Cheng from UCSB visited our group (2013-6)
  • More ...

  • Champion of  2016 DAC LPIRC
    NVIDIA Report
    General moderator of China Fault-Tolerant Computing Conference 2017, China Computer Fedration (440+ attendees)  
     
Newest Publications:
  • We hope more ...
  • Shiqi Lian and Ying Wang's paper are accepted by DAC'17, Congratulations(2017.3)
  • Wenyan Lu's paper are accepted by HPCA'17, Congratulations(2016.10)
  • Ying Wang and  Lili Song's three papers are accepted by DAC'16, Congratulations(2016.6)
  • Ying Wang's two papers are accepted by DAC'15, Congratulations(2015.2)
  • Our work on Data-Aware DRAM Refresh has been accepted by ICCAD'14, Congratulations(2014.8)
  • Hang Lu's work has been accepted by DAC'13, Congratulations(2013.1)
  • Guihai Yan's work has been accepted by HPCA'12, Congratulations(2012.2)
  • Binzhang Fu'work has been accepted by ISCA'11,Congratulations(2011.2)

[Recent Selected Work] Neural Network Accelerator and Robot Processor 
[HPCA2017] Wenyan Lu, Guihai Yan, Jiajun Li, Shijun Gong, Yinhe Han, Xiaowei Li: FlexFlow: A Flexible Dataflow Accelerator Architecture for Convolutional Neural Networks. International Symposium on High Performance Computer Architecture(HPCA) 2017: 553-564
[DAC2017] Shiqi Lian, Yinhe Han, Ying Wang, Yungang Bao, Hang Xiao, Xiaowei Li, Ninghui Sun: Dadu: Accelerating Inverse Kinematics for High-DOF Robots. DAC 2017: 59:1-59:6
[TVLSI2017] Lili Song, Ying Wang, Yinhe Han, Huawei Li, Yuanqing Cheng, Xiaowei Li: STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator. IEEE Trans. VLSI Syst. 25(4): 1285-1296 (2017)
[DAC2016] Ying Wang, Jie Xu, Yinhe Han, Huawei Li, Xiaowei Li: DeepBurning: automatic generation of FPGA-based learning accelerators for the neural network family. DAC 2016: 110:1-110:6
[DAC2016] Lili Song, Ying Wang, Yinhe Han, Xin Zhao, Bosheng Liu, Xiaowei Li: C-Brain: a deep learning accelerator that tames the diversity of CNNs through adaptive data-level parallelization. DAC 2016: 123:1-123:6
[ISCAS2015] Ying Wang, Lili Song, Yinhe Han, Yuanqing Cheng, Huawei Li, Xiaowei Li: A case of precision-tunable STT-RAM memory design for approximate neural network. ISCAS 2015: 1534-1537
[DAC2015] Ying Wang, Yinhe Han, Lei Zhang, Huawei Li, Xiaowei Li: ProPRAM: exploiting the transparent logic resources in non-volatile memory for near data computing. DAC 2015: 47:1-47:6

[Recent Selected Work] Hetergeneous computing, Approximate computing, Near-threshold computing
[TCAD2017] Ying Wang, Yinhe Han, Cheng Wang, Huawei Li, Xiaowei Li: Retention-Aware DRAM Assembly and Repair for Future FGR Memories. IEEE Trans. on CAD of Integrated Circuits and Systems 36(5): 705-718 (2017)
[ASPDAC2017] Xin He, Guihai Yan, Faqiang Sun, Yinhe Han, Xiaowei Li: ApproxEye: Enabling approximate computation reuse for microrobotic computer vision. ASP-DAC 2017: 402-407
[TVLSI2016] Yinhe Han, Jianbo Dong, Kaiheng Weng, Ying Wang, Xiaowei Li: Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation. IEEE Trans. VLSI Syst. 24(1): 92-102 (2016)
[TPDS2016]
Guihai Yan, Jun Ma, Yinhe Han, Xiaowei Li: EcoUp: Towards Economical Datacenter Upgrading. IEEE Trans. Parallel Distrib. Syst. 27(7): 1968-1981 (2016)
[TC2016] Jun Ma, Guihai Yan, Yinhe Han, Xiaowei Li: An Analytical Framework for Estimating Scale-Out and Scale-Up Power Efficiency of Heterogeneous Manycores. IEEE Trans. Computers 65(2): 367-381 (2016) 
[ASPDAC2016] Xin He, Guihai Yan, Yinhe Han, Xiaowei Li: ACR: Enabling computation reuse for approximate computing. ASP-DAC 2016: 643-648
[TVLSI2016] Ying Wang, Yinhe Han, Huawei Li, Xiaowei Li: VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache. IEEE Trans. VLSI Syst. 24(3): 858-870 (2016) 
[ICCAD2014] Yinhe Han, Ying Wang, Huawei Li, Xiaowei Li: Data-aware DRAM refresh to squeeze the margin of retention time in hybrid memory cube. ICCAD 2014: 295-300

[Recent Selected Work] Network On Chip
[DAC2016] Ying Wang, Yinhe Han, Jun Zhou, Huawei Li, Xiaowei Li: DISCO: a low overhead in-network data compressor for energy-efficient chip multi-processors. DAC 2016: 37:1-37:6
[ASPDAC2015] Hang Lu, Guihai Yan, Yinhe Han, Ying Wang, Xiaowei Li: ShuttleNoC: Boosting on-chip communication efficiency by enabling localized power adaptation. ASP-DAC 2015: 142-147
[DAC2013] Hang Lu, Guihai Yan, Yinhe Han, Xiaowei Li: RISO: Relaxed Network-on-Chip Isolation for Cloud Processors, DAC 2013
[ISCA 2011] Binzhang Fu, Yinhe Han, Jun Ma, Huawei Li, Xiaowei Li: An Abacus Turn Model for Time/Space-Efficient Reconfigurable Routing , ISCA 2011.
[ASPAC2011] Cheng Liu, Lei Zhang, Yinhe Han, Xiaowei Li: Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip. ASP-DAC 2011: 357-362
[TVLSI2009] Lei Zhang, Yinhe Han, Qiang Xu, Xiaowei Li, Huawei Li: On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems. IEEE Trans. VLSI Syst. 17(9): 1173-1186 (2009)


Prof. Han received his B. Eng degree from Nanjing University of Aeronautics and Astronautics, Nanjing, China, in 2001, and the M.Eng. and Ph. D degrees in computer science from Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China, in 2003 and 2006, respectively.  He joined Institute of Computing Technology in 2006. He was promoted to Professor in 2014. His work is supported by multiple agencies including the National Natural Science Fund for Outstanding Young Scholars(2015).
Prof. Han leads an architecture group, interested on chip design, computer architecture, specially targeting AI, Robot and Big-data, to provide the compuating engine for these applications. Thre are 20+ students enjoying the research in his group.
Previously, his Ph. D. study was mainly on chip design and test. he received some awards due to his Ph.D. research. These awards included: National Outstanding Dissertation Award Candidates(2008), Outstanding Dissertation Award of China Computer Federation, Outstanding Dissertation Award of Chinese Academy of Sciences, Best Prize of President Scholarship of Chinese Academy of Sciences. He also received the Best Paper Award of the 2003 IEEE Asian Test Symposium and the Best Paper Nomination of the 2005 IEEE Asian South Pacific Design Automation Conference. He was also invited to write a few sections of test compression in the books “VLSI Test Principle and Architecture: Design for Testability” and “System-on-Chip Test Architectures: Nanometer Design for Testability”.

He is elected as the Chair of Young Computer Scientists & Engineers Forum(YOCSEF), China Computer Federation(CCF),2016-2017:
   
 
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Address: No. 6, Kexueyuan South Road, Zhongguancun, Haidian district, Beijing, China60-0717