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胡瑜

撰稿: 摄影: 发布时间:2012年05月22日

科研人员
性别
职称 研究员
所属部门 计算机体系结构国家重点实验室
研究方向 数字系统的可靠性设计与故障诊断
联系方式  huyu@ict.ac.cn 电话:010-62600719
简历

 博士,现为中国科学院计算技术研究所副研究员、博士生导师、中国计算机学会容错计算专业委员会委员、IEEE会员、ACM会员、IEICE会员。分别于1993年、1999年和2003年在电子科技大学(UESTC)获得工学学士、硕士和博士学位。2003年8月进入中国科学院计算技术研究所博士后流动站,2005年8月留所工作至今。近年来主要围绕数字系统的可靠性设计与故障诊断开展研究。2006年获日本学术振兴会Center of Excellence基金资助和香港中文大学Sino British Fellowship Trust资助,先后短期访问日本奈良先端科学技术大学院大学和香港中文大学。曾获得2009年度中国科学院卢嘉锡青年人才奖和2007年度北京市科技新星等多项奖励。

 

 

 

 

 

 

 

代表论著

国际刊物论文
[1]Yu Hu, Yinhe Han, Xiaowei Li, Huawei Li, Xiaoqing Wen, “Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time”, IEICE Transactions on Information and Systems, Vol. E89-D, No.10, 2006, pp. 2616-2625.
[2]Jia Li, Qiang Xu, Yu Hu, Xiaowei Li, “X-Filling for Simultaneous Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing”,  IEEE Transactions on VLSI Systems, Vol. 18, No. 7, 2010, pp. 1081-1092.
[3]Da Wang, Yu Hu, Huawei Li, Xiaowei Li, “The Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor”, Journal of Computer Science and Technology (JCST), Vol. 23, No. 6, 2008, pp. 1037-1046.
[4]Yinhe Han, Yu Hu, Xiaowei Li, Anshuman Chandra, and Huawei Li, “Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for System-on-a-Chip”, IEEE Transactions on VLSI Systems (TVLSI), Vol. 15, No. 5, 2007, pp. 531-540.
[5]Wei Wang, Yu Hu, Yinhe Han, Xiaowei Li, Yousheng Zhang, “Leakage Current Optimization Techniques during Test based on Don’t Care Bits Assignment”, Journal of Computer Science and Technology (JCST), Vol. 22, No. 5, 2007, pp. 673-680.
[6]Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, Anshuman Chandra, and Xiaoqing Wen, “Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores”, IEICE Transactions on Information and Systems, Vol. E88-D, No. 10, 2005, pp. 2126-2134.

国际会议论文
[1]Yu Hu, Xiang Fu, Xiaoxin Fan, and Hideo Fujiwara, “Localized Random Access Scan: Towards Low Area and Routing Overhead”, in the Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Seoul, Korea, 2008, pp.565-570.
[2]Yu Hu, Cheng Li, Jia Li, Yin-He Han, Xiao-Wei Li, Wei Wang, Hua-Wei Li, Laung-Terng (L.-T.) Wang, and Xiao-Qing Wen, “Test Data Compression Based on Clustered Random Access Scan”, in the Proceedings of IEEE Asian Test Symposium (ATS), Fukuoka, Japan, 2006, pp.231-236. 
[3]Yu Hu, Yinhe Han, Xiaowei Li, “Compression/Scan Co-Design to Reduce Test Data Volume, Scan-in Power Dissipation and Test Application Time”, in the Proceedings of IEEE Pacific-Rim Dependable Computing (PRDC), Changsha, China, December 12-14, 2005, pp.175-182. 
[4]Yu Hu, Yinhe Han, Huawei Li, Tao Lv, Xiaowei Li, “Pair Balance-Based Test Scheduling for SOCs”, in the Proceedings of IEEE Asian Test Symposium (ATS) , Kenting, Taiwan, 2004, pp.236-241.
[5]Songjun Pan, Yu Hu, and Xiaowei Li, “IVF: Characterizing the Vulnerability of Microprocessor Structures to Intermittent Faults”, in the Proceedings of IEEE /ACM Conference on Design, Automation and Test in Europe (DATE), Dresden, Germany, 2010, Session. 3.7.  (Best Paper Award Nomination)
[6]Jing Ye, Yu Hu, and Xiaowei Li, “Diagnosis of Multiple Arbitrary Faults with Mask and Reinforcement Effect”, in the Proceedings of IEEE /ACM Conference on Design, Automation and Test in Europe (DATE), Dresden, Germany, 2010, Session. 7.5.
[7]Fei Wang, Yu Hu, Yu Huang, Huawei Li, Xiaowei Li, Jing Ye, “Deterministic Diagnostic Pattern Generation (DDPG) for Compound Defects”, in the Proceedings of IEEE International Test Conference (ITC), Santa Clara, USA, 2008, paper 14.1.
[8]Jia Li, Xiao Liu, Yubin Chen, Yu Hu, Xiaowei Li, Qiang Xu, “On Capture Power-Aware Test Data Compression for Scan-Based Testing”, in the Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, USA, 2008, paper 1C.3. 
[9]Da Wang, Xiaoxin Fan, Xiang Fu, Hui Liu, Ke Wen, Huawei Li, Yu Hu, Xiaowei Li, Rui Li, “The Design-for-Testability Features of A General-Purpose Microprocessor,” in the Proceedings of IEEE International Test Conference (ITC), Santa Clara, USA, 2007, paper 9.2.

承担科研项目情况
在研项目
1.国家自然科学基金青年科学基金课题,大规模多核系统芯片测试压缩方法研究
2.北京市科技新星计划A类课题,嵌入式存储器内建自修复方法研究
3.国家973计划课题:高性能处理芯片的可靠性设计

已结题项目
1.国家自然科学基金SOC重大研究计划面上课题,嵌入式存储器内建自修复方法研究
2.国家自然科学基金SOC重大研究计划重点项目滚动课题,微处理器自修复设计基础技术研究
3.国家863计划探索导向类课题,动态可重构高可靠计算机体系结构及关键实现技术
4.国家863计划探索导向类课题,大规模高可靠片上多处理器的系统结构及实现方法 
5.国家863计划子课题,龙芯2号增强型处理器芯片的可测试性设计及样片测试

 
学科类别 计算机系统结构
专家类别 正高
其他备注 博导 计算机系统结构
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