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Memory Sluice Gate Theory: Have we found a solution for memory wall?

撰稿: 摄影: 发布时间:2016年06月02日
时间:2016年6月3日(周五)上午10:00--11:30
地点:446会议室
摘要:
        The memory-wall problem is a long standing issue facing the computing community. Many believe the memory-wall problem can only be solved with new memory technologies that improve memory device hardware performance. In this talk, we introduce an architectural solution, the memory Sluice Gate Theory, for solving the memory-wall problem. The focus of Sluice Gate Theory is not on hardware peak performance, but the achieved memory stall time. Based on Sluice Gate Theory, a memory system is built to mask the performance gap between CPU and memory devices during the data transfer process. The C-AMAT model is used to calculate the data transfer request/supply ratio at each memory layer (sluice stage) dynamically, and a global control algorithm, named layered performance matching (LPM), is developed to match the data transfer at each memory layer and thus match the overall performance between the CPU and memory system. Data concurrency plays a vital role in the matching and transfer process. Experimental testing is conducted which confirm the theoretical findings, with a 150 times performance improvement and the elimination of memory delay impact in our case studies. Wewill present the concept of Sluice-Gate, the design of C-AMAT and LPM, and discuss the applications and considerations of Sluice-Gate Theory. We will also present some Sluice-Gate-based software solutions for data intensive computing.
主讲人简介:

 Bio-Short version
 
        Dr. Xian-He Sun is a University Distinguished Professor of Computer Science at the Illinois Institute of Technology (IIT). He is the director of the Scalable Computing Software laboratory at IIT and a guest faculty in the Mathematics and Computer Science Division at the Argonne National Laboratory. Before joining IIT, he worked at DoE Ames National Laboratory, at ICASE, NASA Langley Research Center, at Louisiana State University, Baton Rouge, and was an ASEE fellow at Navy Research Laboratories. Dr. Sun is an IEEE fellow and is known for his memory-bounded speedup model, also called Sun-Ni’s Law, for scalable computing. His research interests include data-intensive high performance computing, memory and I/O systems, software system for big data applications, and performance evaluation and optimization. He has over 200 publications and 5 patents in these areas. He is a former IEEE CS distinguished speaker, a former vice chair of the IEEE Technical Committee on Scalable Computing, the past chair of the Computer Science Department at IIT, and is serving and served on the editorial board of most of the leading professional journals in the field of parallel processing. More information about Dr. Sun can be found at his web site www.cs.iit.edu/~sun/
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