The Case for Targeting Open Defects instead of Transition Faults during IC Testing
撰稿：
摄影：
发布时间：2016年03月11日
时间：2016年3月16日（周三）上午10:00-12:00
地点：446会议室
摘要
We make the case that TDF timing tests, even when aggressively applied at-speed, uniquely detect mostly open defects within standard cells. The majority of these defects can also be detected at somewhat slower test speeds without the risk of unnecessary yield loss from test noise. Meanwhile, many other opens that can cause operational failures remain undetected by current LOC, and even LOS, TDF tests. It has recently been shown, in experiments with Cell Aware Tests, that such test escapes can significantly degrade product quality. We argue that it may be better to use two-pattern tests to explicitly target all open faults in the circuit, with the tests being applied at the highest possible speed consistent with limiting yield loss and supporting high test compression efficiency. TDFs will implicitly be covered by such an approach, which can potentially both reduce test costs and improve test quality.
主讲人简介
Adit D. Singh is James B. Davis Distinguished Professor of Electrical and Computer Engineering at Auburn University, where he directs the VLSI Design and Test Laboratory. He has earlier served on the faculty at the University of Massachusetts in Amherst, at Virginia Tech in Blacksburg, and also as a “Guest Professor” at the University of Freiburg, Germany. His technical interests span all aspects of VLSI technology, in particular, integrated circuit test and reliability. He has published over two hundred research papers, served as a consultant to many of the largest semiconductor companies around the world, and holds international patents that have been licensed to industry. He is particularly recognized for his pioneering contributions to statistical methods in test and adaptive testing. He has held leadership roles as General Chair/Co-Chair/Program Chair for dozens of international conferences, and served on the editorial boards of several journals, and on the steering and program committees of many of the major IEEE international test and design automation conferences.
Dr. Singh was elected Fellow of IEEE in 2001 for “contributions to defect based testing and test optimization in VLSI circuits”. He is Golden Core member of the IEEE Computer Society. He served two elected terms (2007-11) as Chair of the IEEE Test Technology Technical Council (TTTC), and on the Board of Governors of the IEEE Council on Design Automation (CEDA) (2011-15).
附件下载：
The Case for Targeting Open Defects instead of Transition Faults during IC Testing
时间：2016年3月16日（周三）上午10:00-12:00
地点：446会议室
摘要
We make the case that TDF timing tests, even when aggressively applied at-speed, uniquely detect mostly open defects within standard cells. The majority of these defects can also be detected at somewhat slower test speeds without the risk of unnecessary yield loss from test noise. Meanwhile, many other opens that can cause operational failures remain undetected by current LOC, and even LOS, TDF tests. It has recently been shown, in experiments with Cell Aware Tests, that such test escapes can significantly degrade product quality. We argue that it may be better to use two-pattern tests to explicitly target all open faults in the circuit, with the tests being applied at the highest possible speed consistent with limiting yield loss and supporting high test compression efficiency. TDFs will implicitly be covered by such an approach, which can potentially both reduce test costs and improve test quality.
主讲人简介
Adit D. Singh is James B. Davis Distinguished Professor of Electrical and Computer Engineering at Auburn University, where he directs the VLSI Design and Test Laboratory. He has earlier served on the faculty at the University of Massachusetts in Amherst, at Virginia Tech in Blacksburg, and also as a “Guest Professor” at the University of Freiburg, Germany. His technical interests span all aspects of VLSI technology, in particular, integrated circuit test and reliability. He has published over two hundred research papers, served as a consultant to many of the largest semiconductor companies around the world, and holds international patents that have been licensed to industry. He is particularly recognized for his pioneering contributions to statistical methods in test and adaptive testing. He has held leadership roles as General Chair/Co-Chair/Program Chair for dozens of international conferences, and served on the editorial boards of several journals, and on the steering and program committees of many of the major IEEE international test and design automation conferences.
Dr. Singh was elected Fellow of IEEE in 2001 for “contributions to defect based testing and test optimization in VLSI circuits”. He is Golden Core member of the IEEE Computer Society. He served two elected terms (2007-11) as Chair of the IEEE Test Technology Technical Council (TTTC), and on the Board of Governors of the IEEE Council on Design Automation (CEDA) (2011-15).