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Adaptive Thread to Core Assignment via Online Program Phase Classification in Asymmetric Multicore Processors (AMP)

撰稿: 摄影: 发布时间:2014年03月09日
时间:2014年3月19日(周三)上午10:00-11:30

地点:4层报告厅

 
摘要
Asymmetric multicore processors (AMPs) have been shown to outperform symmetric ones in terms of performance and performance/watt. The improved performance and power efficiency are achieved when the program threads are matched to their affine cores. Since the computational needs of a program may change during its execution, the best thread to core assignment is not constant. We have therefore, developed an online program phase classification scheme to detect when the current needs of the threads justify a change in the assignment.
 
The architectural differences among the cores in an AMP can never match the diversity that exists among different programs and even between different phases of the same program. We cannot, include only powerful cores in an AMP since they will remain underutilized most of the time, and they are not power efficient when the programs do not exhibit high degree of ILP. Thus, we must expect to see program phases where the designed cores are unable to support the ILP that the program can exhibit. We therefore, propose in this talk a dynamic morphing scheme. This scheme will allow a core to gain control of a functional unit that is ordinarily under the control of a neighboring core, during periods of intense computation with high ILP. This way, we dynamically adjust the hardware resources to the current needs of the application. Results show that combining online phase classification and dynamic core morphing can significantly improve the performance/watt of most multi-threaded workloads.

 
 
主讲人简介
Sandip Kundu is a Professor at the University of Massachusetts at Amherst. Prior to joining academia, he spent several years in industry: first as a Research Staff Member at IBM Research Division and then at Intel Corporation as a Principal Engineer. He has published over 200 research papers in VLSI design and test and holds several key patents including ultra-drowsy sleep mode in processors, and has given more than a dozen tutorials at various conferences. He is a Fellow of the IEEE, Fellow of the Japan Society for Promotion of Science (JSPS) and a Distinguished Visitor of the IEEE Computer Society. He is currently an Associate Editor of the ACM Transactions on Design Automation of Electronic Systems. Previously, he has served as an Associate Editor of the IEEE Transactions on Computers and the IEEE Transactions on VLSI systems. He is/was the Technical Program Chair of ICCD in 2000, Asian Test Symposium in 2011, ISVLSI in 2012 and General chair of ICCD in 2001 and VLSI Design Conference in 2005.
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