Improving Yield and Reliability of Chip Multiprocessors
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摄影：
发布时间：2014年04月06日
时间：2014年4月9日（周三）下午2:30-4:00
地点：计算所7层748会议室
摘要 Device count on a chip has grown exponentially as a consequence of Moore’s law. Producing a completely defect-free chip, even when possible, raises chip cost. ITRS recognizes this and notes that:“Relaxing the requirement of 100% correctness for devices and interconnects may dramatically reduce costs of manufacturing, verification, and test. Such a paradigm shift is likely forced in any case by technology scaling, which leads to more transient and permanent failures of signals, logic values, devices, and interconnects.”
In this talk we describe a scheme for improving yield/reliability of a homogeneous chip multiprocessor (CMP). The solution centers on exploiting the natural redundancy that already exists in multi-core systems by using services from other cores for functional units that are defective in a faulty core. A microarchitectural modification allows a core on a CMP to use another core as a coprocessor to service any instruction that the former cannot execute correctly. This service is accessed to improve yield and reliability, but at the cost of some loss of performance. Our results indicate that when a large and sparingly-used unit such as a floating point arithmetic unit fails in a core, even for a floating point intensive benchmark, we can continue to run each faulty core with help from companion cores with as little as 10% impact to performance and less than 1% area overhead. We will conclude this talk with some observation and recommendation for constructing reliable chip multiprocessors.
主讲人简介
Sandip Kundu is a Professor at the University of Massachusetts at Amherst. Prior to joining academia, he spent several years in industry: first as a Research Staff Member at IBM Research Division and then at Intel Corporation as a Principal Engineer. He has published over 200 research papers in VLSI design and test and holds several key patents including ultra-drowsy sleep mode in processors, and has given more than a dozen tutorials at various conferences. He is a Fellow of the IEEE, Fellow of the Japan Society for Promotion of Science (JSPS) and a Distinguished Visitor of the IEEE Computer Society. He is currently an Associate Editor of the ACM Transactions on Design Automation of Electronic Systems. Previously, he has served as an Associate Editor of the IEEE Transactions on Computers and the IEEE Transactions on VLSI systems. He is/was the Technical Program Chair of ICCD in 2000, Asian Test Symposium in 2011, ISVLSI in 2012 and General chair of ICCD in 2001 and VLSI Design Conference in 2005.
附件下载：
Improving Yield and Reliability of Chip Multiprocessors
地点：计算所7层748会议室
摘要
Device count on a chip has grown exponentially as a consequence of Moore’s law. Producing a completely defect-free chip, even when possible, raises chip cost. ITRS recognizes this and notes that:“Relaxing the requirement of 100% correctness for devices and interconnects may dramatically reduce costs of manufacturing, verification, and test. Such a paradigm shift is likely forced in any case by technology scaling, which leads to more transient and permanent failures of signals, logic values, devices, and interconnects.”
In this talk we describe a scheme for improving yield/reliability of a homogeneous chip multiprocessor (CMP). The solution centers on exploiting the natural redundancy that already exists in multi-core systems by using services from other cores for functional units that are defective in a faulty core. A microarchitectural modification allows a core on a CMP to use another core as a coprocessor to service any instruction that the former cannot execute correctly. This service is accessed to improve yield and reliability, but at the cost of some loss of performance. Our results indicate that when a large and sparingly-used unit such as a floating point arithmetic unit fails in a core, even for a floating point intensive benchmark, we can continue to run each faulty core with help from companion cores with as little as 10% impact to performance and less than 1% area overhead. We will conclude this talk with some observation and recommendation for constructing reliable chip multiprocessors.
主讲人简介
Sandip Kundu is a Professor at the University of Massachusetts at Amherst. Prior to joining academia, he spent several years in industry: first as a Research Staff Member at IBM Research Division and then at Intel Corporation as a Principal Engineer. He has published over 200 research papers in VLSI design and test and holds several key patents including ultra-drowsy sleep mode in processors, and has given more than a dozen tutorials at various conferences. He is a Fellow of the IEEE, Fellow of the Japan Society for Promotion of Science (JSPS) and a Distinguished Visitor of the IEEE Computer Society. He is currently an Associate Editor of the ACM Transactions on Design Automation of Electronic Systems. Previously, he has served as an Associate Editor of the IEEE Transactions on Computers and the IEEE Transactions on VLSI systems. He is/was the Technical Program Chair of ICCD in 2000, Asian Test Symposium in 2011, ISVLSI in 2012 and General chair of ICCD in 2001 and VLSI Design Conference in 2005.