Quality and Yield Enhancement of 3D Integrated Logic and Memory Dies
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摄影：
发布时间：2013年09月02日
时间：2013年9月5日（周四）下午15:00-16:30
地点：446会议室
摘要
Three-dimensional (3D) integration has been considered one of the most promising solutions to extending the life of Moore‘s law in semiconductor industry. However, so far the most critical issue is the high cost resulting from low quality and yield of the TSV and microbump-based 3D stacking process. In this talk we will delineate test issues and challenges for 3D integrated devices, and propose a practical test methodology for 3D integrated logic and memory dies. Our approach covers known-good-die (KGD) test before die/wafer stacking, through-silicon-via (TSV) test for vertical interconnect verification, as well as die test in all layers of the stack after bonding. We will also discuss BIST and BISR for memory/logic die stack.
主讲人简介
Cheng-Wen Wu is Professor of Department of Electrical Engineering, National Tsing Hua University (NTHU), and serving as the General Director of the SOC Technology Center(STC), Industrial Technology Research Institute (ITRI). He received the BSEE degree in 1981 from National Taiwan University, Taipei, Taiwan, and the MS and PhD degrees, both in electrical and computer engineering, in 1985 and 1987, respectively, from the University of California, Santa Barbara (UCSB). In 2004, he became a Fellow of the IEEE.
He is interested in architectures and algorithms with respect to design and testing of reliable VLSI cores and systems, and all testing issues of semiconductor memories. He has received the Best Paper Award of the 2002 IEEE International Workshop on Design & Diagnostics of Electronic Circuits & Systems, the Best Paper Award of the 2003 IEEE Asia & South Pacific Design Automation Conference (ASP-DAC), and the Special Feature Award of the 2003 ASP-DAC University LSI Design Contest. He chaired the Technical Meetings Group of TTTC from 2003 to 2005. He was the Technical Program Chair of the Fifth Asian Test Symposium (ATS'96), General Chair of ATS'00, and the General Chair of 2005 and 2006 IEEE Int. Workshop on Memory Technology (MTDT).
附件下载：
Quality and Yield Enhancement of 3D Integrated Logic and Memory Dies
地点：446会议室
摘要
Three-dimensional (3D) integration has been considered one of the most promising solutions to extending the life of Moore‘s law in semiconductor industry. However, so far the most critical issue is the high cost resulting from low quality and yield of the TSV and microbump-based 3D stacking process. In this talk we will delineate test issues and challenges for 3D integrated devices, and propose a practical test methodology for 3D integrated logic and memory dies. Our approach covers known-good-die (KGD) test before die/wafer stacking, through-silicon-via (TSV) test for vertical interconnect verification, as well as die test in all layers of the stack after bonding. We will also discuss BIST and BISR for memory/logic die stack.
主讲人简介
Cheng-Wen Wu is Professor of Department of Electrical Engineering, National Tsing Hua University (NTHU), and serving as the General Director of the SOC Technology Center(STC), Industrial Technology Research Institute (ITRI). He received the BSEE degree in 1981 from National Taiwan University, Taipei, Taiwan, and the MS and PhD degrees, both in electrical and computer engineering, in 1985 and 1987, respectively, from the University of California, Santa Barbara (UCSB). In 2004, he became a Fellow of the IEEE.
He is interested in architectures and algorithms with respect to design and testing of reliable VLSI cores and systems, and all testing issues of semiconductor memories. He has received the Best Paper Award of the 2002 IEEE International Workshop on Design & Diagnostics of Electronic Circuits & Systems, the Best Paper Award of the 2003 IEEE Asia & South Pacific Design Automation Conference (ASP-DAC), and the Special Feature Award of the 2003 ASP-DAC University LSI Design Contest. He chaired the Technical Meetings Group of TTTC from 2003 to 2005. He was the Technical Program Chair of the Fifth Asian Test Symposium (ATS'96), General Chair of ATS'00, and the General Chair of 2005 and 2006 IEEE Int. Workshop on Memory Technology (MTDT).