High Performance 3D Interconnection Network Design for CMPS
撰稿：
摄影：
发布时间：2013年03月26日
时间：2013年3月28日（周四）下午16:00-17:00
地点：1201会议室
摘要
Chip multiprocessors (CMP) have emerged as a promising microarchitecture for keeping up performance with integration density. Interconnection, providing communications among cores and cache/memory blocks, plays an important role in performance and power of CMP. The advent of three-dimensional (3D) stacked technology provides an opportunity to reduce wire delay and power consumption and allows multiple die fabricated with different processes, such as CMOS, DRAM, nanophotonics, to be stacked together. However the design of 3D Network-on-Chip (NoC) is still in its infancy. There has not been sufficient research on 3D NoCs that fully investigates the four metrics used to evaluate interconnection networks: latency, throughput, power consumption and scalability of the network. In the talk, I will exploit the network topology design for 3D CMP and present a low-diameter 3D network topology using low-radix routers to reduce network latency and power consumption.
主讲人简介
Yi Xu is a researcher at AMD China Lab. She received her B.S. and M.S. in Microelectronics from Nanjing University, Ph.D in Electrical and Computer Engineering from the University of Pittsburgh. She is a member of the IEEE/ACM. Her research interests include efficient interconnection architecture design for 2D/ 3D Chip Multi-Processor (CMP), photonic network designs and cache coherence protocols and she has published a number of papers in top conferences such as ISCA/HPCA.
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High Performance 3D Interconnection Network Design for CMPS
地点：1201会议室
摘要
Chip multiprocessors (CMP) have emerged as a promising microarchitecture for keeping up performance with integration density. Interconnection, providing communications among cores and cache/memory blocks, plays an important role in performance and power of CMP. The advent of three-dimensional (3D) stacked technology provides an opportunity to reduce wire delay and power consumption and allows multiple die fabricated with different processes, such as CMOS, DRAM, nanophotonics, to be stacked together. However the design of 3D Network-on-Chip (NoC) is still in its infancy. There has not been sufficient research on 3D NoCs that fully investigates the four metrics used to evaluate interconnection networks: latency, throughput, power consumption and scalability of the network. In the talk, I will exploit the network topology design for 3D CMP and present a low-diameter 3D network topology using low-radix routers to reduce network latency and power consumption.
主讲人简介
Yi Xu is a researcher at AMD China Lab. She received her B.S. and M.S. in Microelectronics from Nanjing University, Ph.D in Electrical and Computer Engineering from the University of Pittsburgh. She is a member of the IEEE/ACM. Her research interests include efficient interconnection architecture design for 2D/ 3D Chip Multi-Processor (CMP), photonic network designs and cache coherence protocols and she has published a number of papers in top conferences such as ISCA/HPCA.