• 姓名: 张磊
  • 性别: 
  • 职务: 
  • 职称: 副研究员
  • 学历: 博士
  • 通讯地址: 
  • 电话: 
  • 邮政编码: 
  • 传真: 
  • 电子邮件: zlei@ict.ac.cn
    研究领域:
  • 嵌入式片设计,容错计算,物联网
    简历:
  • 男,1981年生,中科院计算所副研究员。2003年毕业于电子科技大学计算机系,获学士学位。2008年,毕业于中科院计算所,获工学博士学位。之后留所工作,就职于系统结构重点实验室。2009年和2010年分别访问香港中文大学和伊利诺伊理工大学,开展国际合作研究。2010年入选计算所“学术百星”。主要研究方向是嵌入式芯片设计和容错计算,在领域著名会议DAC,DATE,ASP-DAC等上发表论文多篇,曾担任IEEE高端测试技术研讨会(WRTLT),嵌入式和多媒体计算(EMC)等多个国际会议的程序委员会委员,担任计算机学报、电子学报、计算机辅助设计与图形学学报等学术刊物的审稿专家。近年来作为骨干成员参与国家863,973,基金重点等项目,主持国家自然科学基金项目一项,计算所创新课题一项。
    代表性论文:
  • L. Zhang, Y. Han, Q. Xu, X. Li and H. Li. "On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17(9), pp.1173-1186, Sep. 2009. J. Dong, L. Zhang, Y. Han, G. Yan, X. Li. "Performance-Asymmetry-Aware Scheduling for Chip Multiprocessors with Static Core Coupling", EuroMicro Journal of Systems Architecture (JSA), 56(10), pp.534-542, Oct. 2010. L. Zhang, Y. Han, H. Li and X. Li. "A Fault Tolerance Mechanism in Chip Many-core Processors", Tsinghua Science and Technology, 12(S1), pp: 169-174, July 2007. L. Zhang, H. Li and X. Li. "A Routing Algorithm for Random Error Tolerance in Network-on-Chip", International Conference on Human-Computer Interaction (HCII), vol. 4, pp: 1211-1220, July 2007. (invited paper) J. Dong, L. Zhang, Y. Han, Y. Wang, X. Li. "Wear Rate Leveling: Lifetime Enhancement of PRAM with Endurance Variation", ACM/IEEE 48th Design Automation Conference (DAC), pp: 972-977, San Diego, CA, USA, June 5-9, 2011. Y. Wang, L. Zhang, Y. Han, H. Li, X. Li. "FlexMemory: Exploiting and Managing Abundant Off-chip Optical Bandwidth", ACM/IEEE Design, Automation and Test in Europe (DATE), pp: 1-6, Grenoble, France, March 14-18, 2011. C. Liu, L. Zhang, Y. Han, X. Li. "A Resilient On-chip Router Design Through Data Path Salvaging", ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp: 437-442, Yokohama, Japan, Jan. 25-28, 2011. C. Liu, L. Zhang, Y. Han, X. Li. "Vertical Interconnects Squeezing in Symmetric 3D Mesh Network-on-Chip", ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp: 357-362, Yokohama, Japan, Jan. 25-28, 2011. Y. Wang, L. Zhang, Y. Han, H. Li, X. Li. "Address Remapping for Static NUCA in NoC-based Degradable Chip-Multiprocessors", IEEE 16th Pacific Rim International Symposium on Dependable Computing (PRDC), pp: 70-76, Tokyo, Japan, Dec. 13-15, 2010. L. Zhang, Y. Yu, J. Dong, Y. Han, S. Ren, X. Li. "Performance-Asymmetry-Aware Topology Virtualization for Defect-Tolerant NoC-based Many-core Processors", IEEE/ACM Design, Automation and Test in Europe (DATE), pp. 1566-1571, Dresden, Germany, March 8-12, 2010. L. Zhang, Y. Han, Q. Xu and X. Li. "Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology", IEEE/ACM Design, Automation and Test in Europe (DATE), pp: 891-896, Munich Germany, March 10-14, 2008. F. Lockom, Z. Li, K. Yue, S. Ghalim, S. Ren, L. Zhang and X. Li. "Hungarian Algorithm Based Virtualization to Maintain Application Timing Similarity for Defect-Tolerant NoC", ACM/IEEE 17th Asia and South Pacific Design Automation Conference (ASP-DAC), Sydney, Australia, Jan.30 - Feb.2, 2012. 李晓维,胡瑜,张磊,鄢贵海著,《数字集成电路容错设计--容缺陷/故障、容参数偏差、容软错误》,科学出版社,2010年4月,北京
    获得荣誉:
    承担项目:
  • 国家自然科学基金项目:基于片上网络的众核处理器容错设计方法研究(项目负责人); 国家自然科学基金项目:高效能自适应处理器体系结构关键技术研究(执行负责人); 计算所创新课题:可重塑处理器原理与关键技术研究(项目负责人); 973项目子课题:大规模高通量计算系统的可靠性设计(主要技术负责人)